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M61522FP
8ch ELECTRONIC VOLUME WITH 8 INPUT SELECTOR
REJ03F0034-0100Z Rev.1.0 Sep.19.2003
Feature
FUNCTION Electronic Volume Input Selector Multi Channel Input External Input REC Output Input ATT Output Gain Control Balance Out FEATURE 8 channel Dependant Electronic Volume with High Voltage Transistor. (0~-99dB/ 1dBstep, -dB) (1) Front L/R channel 8 Input Selector.(Main/Sub) (2) 2 channel Selector Output. All channel 2 Input Selector. 2 External Input.(C/SBLch) 4 Lines REC Output (Both L and R channels) Input ATT (0/-3/-6/-9/-12dB) Output Gain Control (0/+3/+6/+9/+10/+12dB) Built-in Balance Output (for ADC)
Application
Receiver, AV Amp, Mini Stereo etc.
Recommended Operating Condition
Rated Supply Voltage ......AVCC=7.0V(typ), AVEE=-7.0V(typ), DVDD=3.3V(typ)
Rev.1.0, Sep.19.2003, page 1 of 17
M61522FP
System Block Diagram
CLOCK
Multi FRin Multi FLin
LOUT ROUT RECOUTL
1 2 3 4 Lch 5 6 7 8 MA IN R 1 2 3 4 Rch 5 6 7 8 Balance Output R cha nnel InputATT SUB R InputATT Balance Output L channel DVDD DGND MA IN L SUB L AVCC AVEE Multi SBLi n /External INB Multi SLin Multi Cin /External INA
MCU I/F
Output Gain Control
LATCH DATA
FLout
Output Gain Control
FRout
Output Gain Control
Cout
Output Gain Control
SBLout
Output Gain Control
SLout
Multi SBRin Multi SRin Multi SWin
Output Gain Control
SBRout
Output Gain Control
SRout
Output Gain Control
SWout
RECOUTR
GND
Rev.1.0, Sep.19.2003, page 2 of 17
M61522FP
Block Diagram and Pin Configuration (Top View)
38 SBROUT 34 SBLOUT 36 SWOUT 37 SROUT 26 LA TCH 28 CLOCK 33 SLOUT 39 FROUT 32 FLOUT 29 DGND 25 DVDD 35 COUT 30 AVCC
CLOCK Output Gain Control Output Gain Control
FRSELOUT 42 GND 43 FRIN2 44 SBRIN2 45 SRIN2 46 SWIN2 47 CIN2 48 SBLIN2 49 SLIN2 50 FLIN2 51 GND 52 GND 53
(External INA) (External INB)
MCU I/F
DATA LATCH
FRVIN 41
27 DATA
31 GND
40 GND
24 GND 23 FLVIN 22 FLSELOUT 21 GND 20 FRIN1 19 SBRIN1
FLchVOL FRchVOL
Output Gain Control
Output Gain Control
Output Gain Control
Output Gain Control
Output Gain Control
Output Gain Control
18 SRIN1 17 SWIN1 16 CIN1 15 SBLIN1 14 SLIN1 13 FLIN1 12 GND 11 BALANCE R/+
Rch
FRch SBRchVOLSRchVOLSWchVOL
CchVOL
SBLchVOL
SLchVOL
FLch
CIN3 54 GND 56
SBLIN3 55 RECR4 57 RECR3 58 RECR2 59 RECR1 60 ROUT 61 LOUT 62 GND 63 INRH 64
INRG 65 INRF 66 INRE 67 INRD 68 INRC 69 INRB 70 INRA 71 AVEE 72 INLA 73 INLB 74 INLC 75 INLD 76 INLE 77 INLF 78
SUB R
MAIN L MAIN R
10 BALANCE R/9 GND 8 BALANCE L/-
Balance Out InputATT InputATT Lch
7 BALANCE L/+ 6 RECL4 5 RECL3 4 RECL2
S
UB L
3 RECL1 2 GND 1
INLH 80 INLG 79
NC
Rev.1.0, Sep.19.2003, page 3 of 17
M61522FP
Pin Description
PIN No. 1 2,9,12,21,24,31, 40,43,52,53,56,63 3,4,5,6, 57,58,59,60 7,8 10,11 13,51 14,50 15,49 16,48 17,47 18,46 19,45 20,44 22 23 25 29 26,27,28 30 32 33 34 35 36 37 38 39 41 42 54 55 61,62 64,65,66,67,68,69, 70,71 73,74,75,76,77,78, 79,80 72 Name NC GND REC L1,L2,L3,L4 /REC R1,R2,R3,R4 BALANCE L/+,L/BALANCE R/+,R/FLIN1/FLIN2 SLIN1/SLIN2 SBLIN1/SBLIN2 CIN1/CIN2 SWIN1/SWIN2 SRIN1/SRIN2 SBRIN1/SBRIN2 FRIN1/FRIN2 FLSELOUT FLVIN DVDD DGND LATCH,DATA,CLOCK AVCC FLOUT SLOUT SBLOUT COUT SWOUT SBROUT SROUT FROUT FRVIN FRSELOUT CIN3 SBLIN3 ROUT/LOUT INRA,B,C,D,E,F,G,H INLA,B,C,D,E,F,G,H AVEE Function Non-connection terminal Analog Ground Output pin of REC (Lch and Rch) Output pin of L channel Balance Output(+/-) Output pin of R channel Balance Output(+/-) Input pin of FL channel (2 Input Selector) Input pin of SL channel (2 Input Selector) Input pin of SBL channel (2 Input Selector) Input pin of C channel (2 Input Selector) Input pin of SW channel (2 Input Selector) Input pin of SR channel (2 Input Selector) Input pin of SBR channel (2 Input Selector) Input pin of FR channel (2 Input Selector) Output pin of FL channel volume input selector Input pin of FL channel volume Power supply to internal logic circuit Ground of internal logic circuit Input pin of Control trigger/data/clock Positive power supply to internal analog circuit Output pin of FL channel Output pin of SL channel Output pin of SBL channel Output pin of C channel Output pin of SW channel Output pin of SBR channel Output pin of SR channel Output pin of FR channel Input pin of FR channel volume Output pin of FR channel volume input selector External input pinA(Input pin of C channel) External input pinB(Input pin of SBL channel) Output pin of Input selector Input pin of R channel (8 Input Selector) Input pin of L channel (8 Input Selector) Negative power supply to internal analog circuit
Rev.1.0, Sep.19.2003, page 4 of 17
M61522FP
Absolute Maximum Ratings
(Ta=25C, unless otherwise noted)
Symbol Supply voltage Pd K Topr Tstg Parameter Power supply Power dissipation Thermal derating Operating temperature Storage temperature Condition AVCC-AVEE DVDD-GND Ta25C Ta>25C Ratings 7.8 6.0 1250 12.5 -20~+55 -40~+125 Unit V mW mW/C C C
THERMAL DERATINGS (MAXIMU M RATING) 1.5
POWER DISSIPATION Pd(W)
1.0
0.5
0 0
55
25 50 75 100 125 150 AM BIENT TEMPERATURE Ta (C)
Recommended Operating Conditions
(Ta=25C, unless otherwise noted)
Parameter Analog supply voltage (Positive) Analog supply voltage (Negative) Digital supply voltage Logic iHi level input voltage Logic i Li level input voltage Symbol AVCC AVEE DVDD VIH VIL DGND reference DGND reference Condition MIN 4.5 -7.3 3.0 2.4 DGND TYP 7.0 -7.0 3.3 -- -- MAX 7.3 -4.5 3.6 DVDD 0.5 Unit V V V V V
Note1: VEEDGNDRev.1.0, Sep.19.2003, page 5 of 17
M61522FP
Relationship between Data and Clock
H
LA TCH SIGNAL D0 D1 D29 D30 D31 D0
DATA
L H
CLOCK
L H
LA TCH
L
DATA signal is readat the rising edgeof the CLOCK. Serial data (D0 - D31) is loadedat the risingedgeof the LATCH signal.
Clock and Data Timings
tcr
75%
tSC
CLOCK
25% 25%
tr tWHC
tf tWLC
75% 25%
DATA
tr
tf tSD tHD tSL tr
tWHC tf
75% 25%
LATCH
Rev.1.0, Sep.19.2003, page 6 of 17
M61522FP
Timing Definition of Digital Block
Symbol tcr tWHC tWLC tr tf tSD tHD tSL tWHL tSC Parameter Clock cycle time Clock pulse width (iHi level) Clock pulse width (iLi level) Rising time of clock, data and latch Falling time of clock, data and latch Data setup time Data hold time Latch setup time Latch pulse width Clock setup time Limits Min 4 1.6 1.6 -- -- 0.8 0.8 1 1.6 4 typ -- -- -- -- -- -- -- -- -- -- Max -- Unit sec
-- -- 0.4 0.4
-- -- -- -- --
Rev.1.0, Sep.19.2003, page 7 of 17
M61522FP
Data Control Specification
Rev.1.0, Sep.19.2003, page 8 of 17
Three types of input format can be selected by changing the D30/D31slot setting status. (Initialize all data of the3 formats when Digital Powersupply (DVDD) turn on).
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31
Slot 0
Input Selector (MAIN) Input Selector (SUB)
Input ATT
Output Gain Control
FL/FR VOL Input Selector C/SBL VOL Input Selector
All ch REC REC REC REC Output Output Output Output Output VOL Mute 1 2 3 4 Input Selector
SW SR SL SBR
0
0000000
Slot 1
FLch Volume FRch Volume
Cch Volume
SWch Volume
0001
Slot 2
SLch Volume SRch Volume
SBLch Volume
SBRchVolume
0010
M61522FP
Setting Code
(1)Input Selector(MAI N/SUB) (D30=0,D31=0) Setting
MAI N SUB
(4)FL/FR channel Volume Input Se lector (D30=0,D31=0) D2 D6 0 0 1 1 0 0 1 1 0 D3 D7 0 1 0 1 0 1 0 1 0 (6)SW/SR/SL/SBR channel VolumeInput Selector (D30=0,D31=0) Setting D18 0 1 Set ing t Bypass Multi IN1 Multi IN2 D14 0 0 1 D15 0 1 0
D0 D4 0 0 0 0 0 0 0 0 1
D1 D5 0 0 0 0 1 1 1 1 0
AL L OFF A B C D E F G H
(5)C/SBL channel Volume Input Selector (D30=0,D31=0) Set ing t External IN Multi IN1 Multi IN2 D16 0 0 1 D17 0 1 0
(2) Input ATT (D30=0,D31=0) Se tting 0dB -3dB -6dB -9dB -12dB D8 0 0 0 0 1 D9 0 0 1 1 0 D10 0 1 0 1 0
Multi IN1 Multi IN2
(7)All channel Output Mute (D30=0,D31=0) Setting Mute OFF Mute ON D19 0 1
(3)Output Gain Control (D30=0,D31=0) Set ing t 0dB +3dB +6dB +9dB +10dB +12dB D11 0 0 0 0 1 1 D12 0 0 1 1 0 0 D13 0 1 0 1 0 1
(8)REC Output (D30=0,D31=0) RECoutput Setting OFF ON REC1 REC2 REC3 REC4 D20 0 1 D21 0 1 D22 0 1 D23 0 1
It's initial setting when DVDD turn on.
Note : Please don't input except specification data.
Rev.1.0, Sep.19.2003, page 9 of 17
M61522FP
(9)8 channel Volume(FLch,FRch,Cch,SWch:D30=0,D31=1 / SLch,SRch,SBLch,SBRch:D30=1,D31=0) FLch FLch D0 D1 D2 D3 D4 D5 D0 D1 D2 D3 D4 D5 D6 SLch SLch ATT FRch ATT FRch SRch D7 D8 D9 D10 D11 D12 SRch D7 D8 D9 D10 D11 D12 D13 Cch Cch SBLch D14 D15 D16 D17 D18 D19 SBLch D14 D15 D16 D17 D18 D19 D20 SWch SWch SBRch D21 D22 D23 D24 D25 D26 SBRch D21 D22 D23 D24 D25 D26 D27 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB -8dB -9dB -10dB -11dB -12dB -13dB -14dB -15dB -16dB -17dB -18dB -19dB -20dB -21dB -22dB -23dB -24dB -25dB -26dB -27dB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 -28dB -29dB -30dB -31dB -32dB -33dB -34dB -35dB -36dB -37dB -38dB -39dB -40dB -41dB -42dB -43dB -44dB -45dB -46dB -47dB -48dB -49dB -50dB -51dB -52dB -53dB -54dB -55dB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
D6 D13 D20 D27 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Rev.1.0, Sep.19.2003, page 10 of 17
M61522FP
FLch SLch ATT FRch SRch Cch SBLch SWch SBRch -56dB -57dB -58dB -59dB -60dB -61dB -62dB -63dB -64dB -65dB -66dB -67dB -68dB -69dB -70dB -71dB -72dB -73dB -74dB -75dB -76dB -77dB -78dB -79dB -80dB -81dB -82dB D0 D7 D1 D8 D2 D3 D4 D5 D6 ATT FLch SLch FRch SRch Cch SBLch SWch SBRch D0 D7 D1 D8 D2 D3 D4 D5 D6
D9 D10 D11 D12 D13
D9 D10 D11 D12 D13
D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
-83dB -84dB -85dB -86dB -87dB -88dB -89dB -90dB -91dB -92dB -93dB -94dB -95dB -96dB -97dB -98dB -99dB - dB
Note : Please don't input except specification data.
Rev.1.0, Sep.19.2003, page 11 of 17
M61522FP
Electrical Characteristics
Unless otherwise noted, Ta=25C, AVCC=7V, AVEE=-7V, DVDD=3.3V, f=1kHz, Volume=0dB, Input ATT=0dB, Output Gain Control=0dB setting (1) Power supply characteristics
Parameter Analog positive power circuit current Analog negative power Circuit current Digital power circuit current Symbol AIcc AIee DIdd Test condition With AVCC=7V and AVEE=-7V Pin30 pin current, no signal. With AVCC=7V and AVEE=-7V Pin72 pin current, no signal. With DVDD=5V, Pin25 pin current, no signal. Limits min -- -- -- Unit mA mA mA
typ 40 40 3
max 60 60 6
Rev.1.0, Sep.19.2003, page 12 of 17
M61522FP (2) Input/Output characteristics (OVER ALL)
Limits Parameter Input resistance Symbol Rin Test condition 14~19, 45~50pin When each selector chooses a terminal concerned. THD=1%, RL=10kohm Output Gain Contro=+10dB setting Vi=0.3Vrms, FLAT BW: 400Hz~30kHz, f=1kHz, Vo=0.3Vrms, RL=10k BW: 400Hz~30kHz, f=1kHz, Vo=2Vrms, RL=10k Input Pin71,73/Output Pin39,32 Vi=0.3Vrms, JIS-A JIS-A, Rg=0ohm Volume=-dB setting JIS-A, Rg=0ohm Volume=0dB setting Output Pin 7, 8, 10, 11 JIS-A, Rg=0 (Input selector) Pin73~80, Pin71~64 Vo=0.5Vrms, Rg=0, RL=10k, JIS-A (Multi channel/external input selector) Pin51~44, Pin13~20, Pin54,55 Vo=0.5Vrms, Rg=0, RL=10k, JIS-A (Main line) Input Pin71,73/Output Pin32,39 Vo=0.5Vrms, Rg=0, RL=10k, JIS-A (Sub line) Input Pin71,73/Output Pin62,61 Vo=0.5Vrms, Rg=0, RL=10k, JIS-A min 25 typ 50 max 100 Unit k
Maximum output voltage Pass gain Total harmonic distortion
VOM Gv THD1 THD2
3.6 -2.0 -- -- -0.5 -- -- -- --
4.2 0 0.005 0.03 0 2 4 5 -80
-- 2.0 0.05 0.1 0.5 6 12 10 -65
Vrms dB % % dB Vrms Vrms Vrms dB
Channels balance Output noise voltage
CBAL Vono (VOL=-dB) Vono (VOL=0dB) Vonobal (Balance out)
Input selector channel separation
CS1
CS2
--
-80
-65
dB
Crosstalk of mutual channels
CT1
--
-80
-65
dB
CT2
--
-80
-65
dB
Rev.1.0, Sep.19.2003, page 13 of 17
M61522FP (3) 8 channel Volume characteristics Unless otherwise noted, Output Gain Control=0dB setting
Limits Parameter Maximum attenuation Volume gain gang error of mutual channels Cross talk of mutual channels Symbol ATTmax Dvol Test condition Vi=1Vrms, JIS-A, VOL=- Pin32,33,34,35,36,37,38,39 Output, Volume=0dB setting Vo=0.5Vrms, RL=10k , JIS-A, Rg=0 min -- -0.5 typ -100 0 max -95 +0.5 Unit dB dB
CTvol
--
-80
-65
dB
Rev.1.0, Sep.19.2003, page 14 of 17
LOUT
62
M61522FP
BALANCE OUTPUT L+
7 29 25 30 72 8 11 10
L-
R+
R-
DVDD AV CC AV EE -7V DGND +3.3V +7V
INLA
SUB L
73
INLB
Input ATT 0/-3/-6/-9/-12dB
26
74
Internal Block Diagram
RECL4 RECL3 RECL2 RECL1
INLC
3 4 5 6
75
INLD
MCU I/F
76
Rev.1.0, Sep.19.2003, page 15 of 17
INLE
0/-3/-6/-9/-12dB
LA TCH
27
77
INLF
Input ATT
FLch VolumeInputSe lector
78
DATA
28
INLG
79
CLOCK
INLH
MAI N L
51 16 48 54 15 49 55 17 47 14 50 18 46 19 45 20 44 42
FRch VolumeInputSe lector
Cch Volume InputSe lector
80 13 22 23
0~-99dB
32
FLOUT
0/+3/+6/+9/+10/+12dB Output Gain Control 0~-99dB
ROUT
63
FLIN1 FLIN2 CIN1 CIN2 CIN3
(External INA)
SBLch Volume InputSe lector
1
NC
35
COUT
0/+3/+6/+9/+10/+12dB Output Gain Control 0~-99dB
SUB R
INRA
(External INB)
71
SBLIN1 SBLIN2 SBLIN3 SWIN1 SWIN2 SLIN1 SLIN2 SRIN1 SRIN2
33
0~-99dB
SLch Volume InputSe lector
SBLOUT
0/+3/+6/+9/+10/+12dB Output Gain Control
40 2 36
0~-99dB
SRch Volume InputSe lector
SWch Volume InputSe lector
INRB
70
43
RECR4 RECR3 RECR2 RECR1
INRC
60 59 58 57
69
SWOUT
0/+3/+6/+9/+10/+12dB Output Gain Control
9 12 33
0~-99dB
SBRch Volume InputSe lector
52 53
INRD
68
GND SLOUT
0/+3/+6/+9/+10/+12dB Output Gain Control
INRE
67
21 37
0~-99dB
56
INRF
66
0/+3/+6/+9/+10/+12dB Output Gain Control
SROUT
38 41
0~-99dB
24 31
63
INRG
MAI N R
65
SBROUT
0/+3/+6/+9/+10/+12dB Output Gain Control
INRH
64
SBRIN1 SBRIN2 FRIN1 FRIN2
39
FROUT
0/+3/+6/+9/+10/+12dB Output Gain Control
M61522FP
Application Example
R SBRSR SW C SBL SL L AVCC 7V
40 39 38 37 36 35 34 33 32 31 30
DGND
MCU
28 26 27
DVDD 3.3V
25
29
DATA LATCH
41 42 43 RIN2
47k Output Gain Control Output Gain Control
CLOCK
24 23 22 21 RIN1
47k
MCU I/F
44 45 46 47 48 49 50
FRch SBRchVOLSRchVOLSWchVOL CchVOL SBLchVOL SLchVOL FLch Output Gain Control Output Gain Control Output Gain Control Output Gain Control Output Gain Control Output Gain Control FLchVOL FRchVOL
SBRIN2 SRIN2 SWIN2 CIN2 SBLIN2 SLIN2 LI N2
47k
20 19 18 17 16 15 14 13 12 11
Rch
SBRIN1 SRIN1 SWIN1 CIN1 SBLIN1 SLIN1 LI N1
47k
51 52 53
CIN3
(External INA)
54 55 56
Balance Out InputATT InputATT Lch
+
SBLIN3
(External INB)
- ADC -
10 9 8 7 6 5
MAIN L
RECR4 RECR3 RECR2 RECR1 ROUT LOUT
57 58 59 60 61 62 63
+ RECL4 RECL3 RECL2 RECL1
4
UB L
SUB R
MAIN R
S
3 2 1 NC
INRH
64
47k
65
66
67
68
69
70
71
72
73
74
75
76
77
79
47k
47k
47k
47k
47k
47k
47k
47k
47k
47k
47k
47k
47k
78
47k
AVEE -7V
INRF INRE INRG INRC INRD INRB INLE INLC INLF INRA INLG INLD INLA INLH INLB
Rev.1.0, Sep.19.2003, page 16 of 17
80
47k
M61522FP
80P6N-A
JEDEC Code -- MD Weight(g) 1.58 Lead Material Alloy 42
MMP
Plastic 80pin 1420mm body QFP
EIAJ Package Code QFP80-P-1420-0.80
e
Package Dimensions
HD D
65 64
E
24 41
25
40
HE
A2
c
x
M
A1
Rev.1.0, Sep.19.2003, page 17 of 17
1
b2
I2 Recommended Mount Pad Symbol
A L1
A A1 A2 b c D E e HD HE L L1 x y L
Detail F
F e
b
y
b2 I2 MD ME
Dimension in Millimeters Min Nom Max -- -- 3.05 0.1 0.2 0 2.8 -- -- 0.3 0.35 0.45 0.13 0.15 0.2 13.8 14.0 14.2 19.8 20.0 20.2 0.8 -- -- 16.5 16.8 17.1 22.5 22.8 23.1 0.4 0.6 0.8 1.4 -- -- -- -- 0.2 0.1 -- -- 0 10 -- 0.5 -- -- 1.3 -- -- 14.6 -- -- -- -- 20.6
ME
80
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1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
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Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001
http://www.renesas.com
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